The present invention relates generally to semiconductor-on-insulator (SOI) devices and to methods of forming the same and, more particularly, to SOI devices and methods for forming same which promote the removal of heat from the SOI devices.
Traditional semiconductor-on-insulator (SOI) integrated circuits typically have a silicon substrate with a buried oxide (BOX) layer disposed thereon. An active silicon layer is disposed on the opposite side of the BOX layer from the silicon substrate. Within the active silicon layer, active devices, such as transistors, are formed in active regions. The size and placement of the active regions are defined by shallow trench isolation (STI) regions. As a result of this arrangement, the active devices are isolated from the silicon substrate by the BOX layer. In addition, a body region of each SOI transistor does not have body contacts and is therefore xe2x80x9cfloating.xe2x80x9d
Such SOI structures offer potential advantages over bulk chips for the fabrication of high performance integrated circuits for digital circuitry. Such digital circuitry is typically made from partially-depleted metal oxide semiconductor field effect transistors (MOSFETs). These SOI structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to the floating body charging effects. These performance gains result from: a) no connection being made to the channel region, and b) charging of the floating body providing access toward a majority of carriers which dynamically lowers the threshold voltage and increased drain current. Devices, such as metal oxide silicon field effect transistors (MOSFETs), have a number of advantages when formed on SOI wafers versus bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance that results in improved speed performance at higher-operating frequencies; reduced N+ to P+ spacing and thus higher packing density due to ease of isolation; absence of latch-up; lower voltage applications; and higher xe2x80x9csoft errorxe2x80x9d upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Although there are significant advantages associated with SOI technology, there are some disadvantages as well. For example, poor heat removal from electrical devices on an SOI substrate is a significant disadvantage. Electrical devices generate heat, and the inability to remove or dissipate the heat results in poor and/or inconsistent performance of the electrical devices, or even in some instances device and/or substrate degradation.
The poor heat removal for electrical devices on SOI substrates is primarily because of the buried oxide insulation layer. More specifically, the buried oxide insulation layer has a markedly lower thermal conductivity than the thermal conductivity of conventional bulk silicon (typically used as semiconductor substrates), which typically surrounds semiconductor devices. For example, the thermal conductivity of silicon dioxide in the BOX layer is about 1.4 W/mxc2x0 C. while the thermal conductivity of conventional bulk silicon is about 150 W/mxc2x0 C. As a result, the buried oxide layer undesirably thermally insulates the electrical device region in SOI substrates.
In view of the aforementioned disadvantages, there is a need for SOI devices of improved quality, particularly SOI devices having improved heat removal characteristics, and more efficient methods of making such SOI devices.
According to the invention, a silicon-on-insulator (SOI) device comprises a substrate having a buried oxide layer (BOX) disposed on the upper surface of the substrate. The BOX has an upper surface and a cavity extending from the upper surface partially therein. An active layer is disposed on the BOX layer. The active layer extends into the cavity. In a conventional MOSFET or transistor formed on the active layer, there is a source, a drain, and a body disposed therebetween, wherein the body extends into and generally fills the cavity.
According to the invention, the cavity has a bottom surface spaced a distance xe2x80x9cxxe2x80x9d from the lower surface of the BOX layer and the BOX layer has a width xe2x80x9cwxe2x80x9d, wherein xe2x80x9cxxe2x80x9d is less than xe2x80x9cwxe2x80x9d. The bottom surface of the cavity is spaced a distance xe2x80x9cxxe2x80x9d of 100 xc3x85 to 500 xc3x85 from the lower surface of the BOX layer. Also, the distance xe2x80x9cxxe2x80x9d is from 10 percent to 25 percent of the width xe2x80x9cwxe2x80x9d of the BOX layer. Moreover, the width xe2x80x9cwxe2x80x9d of the BOX layer is from about 1000 xc3x85 to about 2000 xc3x85.
According to the invention, a method of fabricating the silicon-on-insulator (SOI) device having a substrate with a lower surface of a buried oxide (BOX) layer disposed thereon is disclosed. The method comprising the steps of providing a silicon substrate with a BOX layer; depositing a nitride layer on surface of the BOX layer followed by depositing a gate mask layer on nitride layer; removing a central section of nitride layer where gate is to be located; stripping away the gate mask; controlled etching of the central section of the Box layer to form a cavity; and removing the first and second nitride regions.
Further according to the invention, the method includes the step of growing/depositing an active layer of silicon on the BOX layer whereby the active layer extends into the cavity. The method can include doping the active layer to form a source, a drain, and a body disposed therebetween so that the body extends into the cavity. The method can further including the steps of forming STI regions at opposite ends of the active layer; and depositing gate oxide on outer surface of the body and on the outer surface of the STI regions. Also, the method includes depositing the silicon using epitaxy.
According to the invention, a method is provided for fabricating an intermediate wafer used in the construction of a silicon-on-insulator (SOI) device having a silicon substrate with a lower surface of a buried oxide layer (BOX) disposed thereon. The method comprising the steps of: providing a silicon substrate with a BOX layer; depositing a nitride layer on surface of the BOX layer followed by depositing a gate mask layer on nitride layer; removing a central section of nitride layer where gate is to be located; stripping away the gate mask; controlled etching of the central section of the Box layer to form a cavity; and removing the first and second nitride regions.